1. Field of the Invention
The present invention generally relates to an analog-to-digital converter (ADC), and more particularly to a multi-bit per cycle successive approximation register (SAR) ADC.
2. Description of Related Art
A successive approximation register (SAR) analog-to-digital converter (ADC) is a type of ADC that converts an analog signal to a digital code equivalent of the analog signal. FIG. 1 shows a schematic diagram illustrating a conventional SAR ADC. The SAR ADC performs conversion by comparison and searching through all possible quantization levels, i.e., binary search, to obtain a digital output. The SAR ADC requires less silicon area and the associated cost than other ADC architectures. However, as the conventional SAR ADC as exemplified in FIG. 1 converts one bit per cycle, it therefore does not fit for high speed applications.
In order to speed up the operation of the SAR ADC, a 2-bit per cycle (or 2b/cycle) SAR ADC is proposed. FIG. 2 shows a block diagram illustrating a conventional 2b/cycle SAR ADC. Compared with the 1b/cycle SAR ADC of FIG. 1, the 2b/cycle SAR ADC involves triple capacitive ADCs (designated as C-net) and thus causes triple loading for a previous stage (e.g., a source follower made of a current source 11 and a p-type transistor 12) in the SAR ADC. Moreover, as more comparators 13 are used in the 2b/cycle SAR ADC (FIG. 2) than the 1b/cycle SAR ADC (FIG. 1), mismatch issue among the comparators in the 2b/cycle SAR ADC need be resolved.
For the foregoing reasons, a need has arisen to propose a novel multi-bit per cycle SAR ADC to overcome the disadvantages as mentioned above.